Gate driving circuit and driving method thereof, display substrate, and display device

ABSTRACT

The present invention is related to a gate driving circuit for a display device. The gate driving, circuit may comprise x stages of driving shift register units connected in series. Each of the driving shift register units may comprise an input terminal, an output terminal, and a reset terminal. The input terminal may comprise a first input port and a second input port. A row of pixel units driven by the driving shift register unit of the m-th stage may have the same polarity distribution as a row of pixel units driven by the driving shift register unit of the (m−N)-th stage, N is an integer greater than 1, m is an integer and N+1&lt;m≤x.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the filing date of Chinese PatentApplication. No. 201610934970.8 filed on Nov. 1, 2016, the disclosure ofwhich is hereby incorporated by reference.

TECHNICAL FIELD

This invention relates to a display technology, and more particularly,to a gate driving circuit and a driving method thereof, a displaysubstrate, and a display device.

BACKGROUND

A driving circuit of a liquid crystal display panel includes a gatedriving circuit and a source driving circuit. The gate driving circuitcomprises a plurality of shift register units connected in series, eachof the shift register units corresponding to a row of pixel units,During a display process, the plurality of the shift register unitssuccessively outputs a scan signal to turn on the corresponding row ofpixel units. The source driving circuit then supplies data signals tothe corresponding row of pixel units that are turned on so as to chargethe pixel units.

In order to achieve fast charging of pixel units to meet high resolutionrequirements of a product, an output time of each shift register unit isusually made to exceed a time required for the corresponding row ofpixel units to be turned on. Furthermore, there is an. overlap betweenoutput times of different shift register units so that the turn-on timesbetween the corresponding rows of the pixel units have an overlap.

BRIEF SUMMARY

Accordingly, one example of the present disclosure is a gate drivingcircuit. The gate driving circuit may comprise x stages of driving shillregister units connected in series, Each of the driving shift registerunits may comprise an input terminal, an output terminal, and a resetterminal. The input terminal may comprise a first input port and asecond input port. A first input port of a driving shift register unitof the m-th stage may be connected to an output terminal of a drivingshift register unit of the (m-1)-th stage. A second input port of thedriving shift register unit of the m-th stage may be connected to anoutput terminal of a driving shift register unit of the (m−N-1)-thstage. N is an integer greater than 1, x is an integer, in is aninteger, and N+1<m≤x.

A row of pixel units driven by the driving shift register unit of them-th stage may have the same polarity distribution as a row of pixelunits driven by a driving shift register unit of the (m−N)-th stage.

The gate driving circuit may further comprise N stages of start shillregister units connected in series. An input terminal of a start shiftregister unit of the p stage may be connected to an output terminal of astart shift register unit of the (p−1)-th stage, wherein p is an integerand 1<p≤N. N may be 2.

The gate driving circuit may further comprise a start signal terminal.An input terminal of a start shift register unit of the first stage maybe connected to the start signal terminal. A. second input port of adriving shift register unit of the first stage may be connected to thestart signal terminal. A first input port of the driving shift registerunit of the first stage may be connected to an output terminal of astart shift register unit of the Nth stage. A second input port of adriving shift register unit of the q-th stage may be connected to anoutput terminal of a start shift .register unit of the (q−1) stage. q isan integer and 1<q≤N+1.

An output terminal of the start shift register unit of the p stage maybe connected to a reset terminal of the start shift register unit of the(p−1)-th stage. A reset terminal of the start shift register unit of theN stage may be connected to an output terminal of a driving shillregister unit of the first stage. An output terminal of the drivingshift register unit of the m-th stage may be connected to a resetterminal of the driving shift register unit of the (m−1)th stage.

Each of the driving shift register units may be configured to output aneffective signal after at least one of the first input port and thesecond input port receives an effective signal.

The gate driving circuit May further comprise €t first clock supplyterminal and a second clock supply terminal. The first clock supplyterminal and the second clock supply terminal may be configured toprovide clock signals with opposite phases. A first clock signalterminal of a start shift register unit of the odd-numbered stage andthat of a driving shift register unit of the odd-numbered stage may beconnected to the first clock supply terminal respectively. A secondclock signal terminal of the start shift register unit of theodd-numbered stage and that of the driving shift register unit of theodd-numbered stage may be connected to the second clock supply terminalrespectively. A first clock signal terminal of a start shift registerunit of the even-numbered stage and that of a driving shift registerunit of the even-numbered stage may be connected to the second clocksupply terminal respectively. A second clock signal terminal of thestart shift register unit of the even-numbered stage and that of thedriving shift register unit of the even-numbered stage may be connectedto the first clock supply terminal respectively.

Each of the start shift register units may include an input module, apull-up module, a reset module, and a pull-down module. The input moduleof the start shift register unit may include a fourth transistor. A gateand a first terminal of the fourth transistor may be connected to theinput terminal of the start shift register unit. A second terminal ofthe fourth transistor may be connected to a pull-up node of the startshift register unit.

Another example of the present disclosure is a display substratecomprising a plurality of rows of pixel units and the gate drivingcircuit according to one embodiment of the present disclosure. Each ofthe driving shift register units corresponds to one of the plurality ofrows of the pixel units respectively.

Another example of the present disclosure is a display device comprisingthe display substrate according to one embodiment of the presentdisclosure.

Another example of the present disclosure is a driving method of thegate driving circuit according to one embodiment of the presentdisclosure. The driving method may comprise, in each cycle of displaycycle, providing an effective signal to the input terminal of the startshift register unit of the first stage, and providing an effectivesignal to the second input port of the driving shift register unit ofthe first stage. The driving method may further comprise providing twoclock signals with opposite phases by the first clock supply terminaland the second clock supply terminal respectively.

Another example of the present disclosure is a driving shift registerunit. The driving shift register unit may comprise an input terminal, anoutput terminal, a reset terminal, a first clock signal terminal, and avoltage terminal. The input terminal may comprise a first input port anda second input port. The driving shift register may further comprise aninput module, a pull-up module, and a reset module. The input module maybe connected to the input terminal and a pull-up node respectively. Thepull-up module may be connected to the pull-up node, the first clocksignal terminal, and the output terminal respectively. The reset modulemay be connected to the reset terminal, the pull-up node, the outputterminal, and the voltage terminal respectively. The input module may beconfigured to provide an effective signal to the pull-up node when theinput terminal receives an effective signal, the pull-up node being aconnection node of the input module and the pull-up module. The pull-upmodule may be configured to electrically connect the first clock signalterminal and the output terminal when the pull-up node receives aneffective signal. The reset module may be configured to electricallyconnect the pull-up node and the output terminal to the voltage terminalrespectively when the reset terminal receives an effective signal.

The driving shift register unit may further comprise a second clocksignal terminal and a pull-down module connected to the second clocksignal terminal, the pull-up node and the output terminal respectively.The pull-down module may be configured to electrically connect thepull-up node and the output terminal to the voltage terminalrespectively when the second clock signal terminal receives an effectivesignal.

The input module of the driving shift register unit may include a firsttransistor, a second transistor and a third transistor. A gate and afirst terminal of the first transistor may be connected to the firstinput port. A gate and a first terminal of the second transistor may beconnected to the second input port. A second terminal of the, firsttransistor may be connected to a second terminal of the secondtransistor. A first terminal and a gate of the third transistor may beconnected to the second terminal of the second transistor respectively.A second terminal of the third transistor may be connected to thepull-up node of the driving shift register unit.

The pull-up module of the driving shift register unit may include afifth transistor and a storage capacitor. A first terminal of thestorage capacitor may be connected to the pull-up node. A secondterminal of the storage capacitor may be connected to the outputterminal. A gate of the fifth transistor may be connected to the firstterminal of the storage capacitor. A first terminal of the fifthtransistor may be connected to the first clock signal terminal. A secondterminal of the fifth transistor may be connected to the outputterminal.

The reset module of the driving shift register unit may include a sixthtransistor and a seventh transistor. A gate of the sixth transistor anda gate of the seventh transistor may be connected to the reset terminalrespectively. A first terminal of the sixth transistor may be connectedto the pull-up node. A first terminal of the seventh transistor may beconnected to the output terminal. A second terminal of the sixthtransistor and a second terminal of the seventh transistor may beconnected to the voltage terminal respectively.

The pull-down module of the driving shift register unit may include aneighth transistor, a ninth transistor, a tenth transistor, an eleventhtransistor, a twelfth transistor, a thirteenth transistor, a fourteenthtransistor, and a fifteenth transistor. A gate of the thirteenthtransistor may be connected to the second clock signal terminal. A firstterminal of the thirteenth. transistor may be connected to the inputterminal. A second terminal of the thirteenth transistor may beconnected to the pull-up node. A gate and a first terminal of the ninthtransistor may be connected to the second clock signal terminalrespectively. A second terminal of the ninth transistor may be connectedto a gate of the fifteenth transistor. A first terminal of the fifteenthtransistor may be connected to the second clock signal terminal. Asecond terminal of the fifteenth transistor may be connected to a lintterminal of the fourteenth transistor. A gate of the fourteenthtransistor may be connected to the pull-up node. A second terminal ofthe fourteenth transistor may be connected to the voltage terminal. Agate of the eighth transistor may be connected to the pull-up node. Afirst terminal of the eighth transistor may be connected to a gate ofthe fifth transistor. A second terminal of the eighth transistor may beconnected to the ineffective signal terminal. A gate of the tenthtransistor and a gate of the eleventh transistor may be connected to asecond terminal of the fifteenth transistor. A first terminal of thetenth transistor may be connected to the pull-up node. A first terminalof the eleventh transistor may be connected to the output terminal. Asecond terminal of the tenth transistor and a second terminal of theeleventh transistor may be connected to the voltage terminal. A gate ofthe twelfth transistor may be connected to the second clock signalterminal. A first terminal of the twelfth transistor may be connected tothe output terminal. A second terminal of the twelfth transistor may beconnected to the voltage terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other objects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich.

FIG. 1 is a timing chart of an output signal of a gate driving circuitin conventional art.

FIG. 2 is a schematic view of polarity distribution of pixel units oftwo continuous frames in a dot inversion driving mode (a) a first frame,(b) a second frame.

FIG. 3 is a schematic structural view of a gate driving circuitaccording to one embodiment of the present invention.

FIG. 4 is a signal timing diagram during operation of the gate drivingcircuit of FIG. 3 according to one embodiment of the present invention.

FIG. 5 is a block diagram of a module structure of a shift register unitaccording to one embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a start shift register unitaccording to one embodiment of the present invention.

FIG. 7 is a signal timing diagram in operation of a start shift registerunit according to one embodiment of the present invention.

FIG. 8 is a schematic structural diagram of a driving shift registerunit according to one embodiment of the present invention.

FIG. 9 is a signal timing diagram in operation of a driving shiftregister according to one embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is described with reference to embodiments of theinvention. Throughout the description of the invention, reference ismade to FIGS. 1-9. When referring to the figures, like structures andelements shown throughout are indicated with like reference numerals.

FIG. 1 shows a timing chart of an output signal of a gate drivingcircuit in conventional art. Specifically, as shown in FIG. 1, a shiftregister unit of the first-stage SR1 outputs a high level between phaset1 to phase t3 to turn on the first row of pixel units. A shift registerunit of the second stage SR2 outputs a high level between phase t2 tophase t4 to turn on the second row of pixel units, and so on. A sourcedriving circuit provides corresponding data signals for the first row ofpixel units at time t3 so that the first row of pixel units isdisplayed. At the same time, in the t3 phase, SR2 and SR3 also output ahigh level, the second row and the third row of pixel units are open, sothat the data signals are also written to the second and third rows ofthe pixel units. The t3 phase corresponds to the pre-charging phase forthe second and third rows of the pixel units. Thus, in a case wherepolarity distributions of the rows of the pixel units are the same, whendata signals for display are provided for the second and third rows ofpixel units, since pre-charging has been performed, the second and thirdrows of the pixel units can quickly reach corresponding data signalvoltages. As a result, writing speed of the data signals is improved.This is especially beneficial for a device having a large size and ahigh resolution.

However, a dot inversion driving mode is widely used due to itsexcellent display effect. As shown in FIG. 2 (a) and FIG. 2(b), polarityof every pixel units is inverted between adjacent frames in the dotinversion driving mode. Polarity of two adjacent pixel units in the samecolumn is also inverted in each frame. In this case, if the drivingmethod in FIG. 1 is adopted, the signals written into the pixel units ofthe second row in the pre-charging process are opposite in polarity tothe actually required data signals. This can result in reversepre-charging to produce stripes and other adverse display effects.

FIG. 3 shows a schematic structural view of a gate driving circuitaccording to one embodiment of the present invention. The gate drivingcircuit comprises driving shift register units of x stages connected inseries such as D_SR1, D_SR2, etc. x is the total number of the drivingshift register units in the gate driving circuit.

As shown in FIG. 3, the driving shift register unit comprises an inputterminal IN, an output terminal OUT, and a reset terminal Reset. Theinput terminal IN comprises a first input port IN1 and a second inputport IN2. In one embodiment, a first input port IN1 of a driving shiftregister unit of the m-th stage is connected to an output terminal OUTof a driving shift register unit of the (m−1)-th stage. A second inputport IN2 of a driving shift register unit of the m-th stage is connectedto an output terminal OUT of a driving shift register unit of the(m−N−1)-th stage. N is an integer greater than 1. x is an integergreater than N+1. m is an integer and N+1<m≤x. The stage at which adriving shift register unit is designated is determined by the order ofthe driving shift register unit located in all the driving shiftregister units.

The driving shift register unit is configured to output an effectivesignal after at least one of the first input port IN1 and the secondinput port IN2 thereof receives an effective signal. In the presentinvention, when a second input port IN2 of a driving shift register unitreceives an effective signal, the driving shift register unit outputs acorresponding effective signal, which is referred as a second effectivesignal. When a first input port IN1 of a driving shift register unitreceives an effective signal and a second input port IN2 thereof doesnot receive an effective signal, the driving shift register unit outputsa corresponding effective signal, which is referred as a first effectivesignal. Each stage of the driving shift register unit outputs a secondeffective signal earlier than a first effective signal. The secondeffective signal is used for turning on the corresponding row of pixelunits to pre-charge the pixel units. The first effective signal is usedfor turning on the corresponding row of pixel units to write datasignals into the pixel units for display.

Each driving shill register unit is used for driving a row of pixelunits of a display substrate. Polarity of a pixel unit is determined bythe relative relationship between a voltage of a pixel electrode of thepixel unit and a common voltage during one frame of image display. Whenthe voltage of the pixel electrode is greater than the common voltage,the pixel unit exhibits positive polarity. When the voltage of the pixelelectrode is less than the common voltage, the pixel unit exhibitsnegative polarity. That polarity distribution of two rows of pixel unitsis the same means that polarity of two pixel units on any one column ofthe two rows of the pixel units is the same.

In one embodiment, a row of pixel units driven by the driving shiftregister unit of the m-th stage have the same polarity distribution as arow of pixel units driven by the driving shift register unit of the(m−N)-th. stage.

FIGS. 2 (a) and (b) show a schematic view of polarity distribution ofpixel units of two continuous frames in a dot inversion driving moderespectively. FIG. 2(a) represents the first or prior frame and FIG.2(b) represents the second or later frame. The gate driving circuitaccording to one embodiment of the present invention is applicable to adisplay device of the dot inversion driving mode, which has excellentdisplay effect. In this case, N can be 2. As shown in FIGS. 2(a) and(b), all odd-numbered rows of pixel units driven by driving shiftregister units of the odd-numbered stages respectively have the samepolarity distribution in both frames. All even-numbered rows of pixelunits driven by driving shift register units of the even-numbered stagesrespectively have the same polarity distribution in both frames. Ofcourse, N can also be integers such as 4, 6, and 8. It should be notedthat the present invention is not limited to the dot inversion drivingmode in FIG. 2, and can also be used in other forms of inversion drivingmode. For example, when an arbitrary fame age is displayed, polaritydistribution of two adjacent pixel units of the same row is the same,and polarity distribution of a plurality of pixel units in the samecolumn are “. . . +, +, −, −, +, +, . . . ”. In this case, N may be 4, 8or 12 etc. so that a row of pixel units driven by the driving shiftregister unit of the m-th stage have the same polarity distribution as arow of pixel units driven by the driving shift register unit of the(m−N)-th stage.

In one embodiment, the second input port IN2 of the driving shiftregister unit the m-th stage D_SR (m) and the first input port IN I ofthe driving shift register unit of the (m−N)-th stage D_SR (m−N) areboth connected with the output terminal OUT of the driving shiftregister unit of the (m−N−1)-th stage D_SR (m−N−1). Thus, when a firsteffective signal is outputted from the driving shift register unit ofthe (m−N−1)-th stage D_SR (m−N−1), the first input port IN1 of thedriving shift register unit of the (m−N)-th stage D_SR (m−N) and thesecond. input port IN2 of the driving shift register unit of the m-thstage D_SR (m) simultaneously receive an effective signal. As a result,the driving shift register unit of the (m−N)-th stage D_SR (m−N) outputsa first effective signal to turn on the (m−N)-th row of pixel units.Then, a source driving circuit writes data signals to the (m−N)-th. rowof pixel units, and the (m−N)-th row of pixel units are displayed. Atthe same time, the driving shift registering unit of the m-th stage D_SR(m) outputs a second effective signal to turn on the m-th row of pixelunits so that the data signals written to the (m−N)-th row of pixelunits are also written in the m-th row of the pixel units. This isequivalent to pre-charge the m-th mw of the pixel units. Since polaritydistributions of the pixel units of the m-th row and the (m−N)-th roware the same, polarity of the signals of the pixel units on the m-th rowat the time of pre-charging is the same as polarity of the signals. thatare subsequently written to the pixel units of the row for display. Assuch, reverse pre-charging does not occur here. Accordingly, occurrenceof strips and the like can be reduced while speed of writing datasignals for display is increased, thereby improving the display quality.

In driving shift register units of any two adjacent stages, a firstinput port IN1 of a driving shift register unit of the later stage isconnected to an output terminal OUT of a driving shift register unit ofa prior stage. The second input port IN2 of the driving shift registerunit of the m-th stage is connected to the output terminal OUT of thedriving shift register unit of the (m−N−1)-th stage. Thus, the secondinput port IN2 of the driving shift register unit of the m-th stageD_SRm is also connected to the first input port of the driving shiftregister unit of the (m−N)-th stage D_SR (m−N). m is an integer greaterthan N+1 and less than or equal to which is the total number of thedriving shift register units.

In one embodiment, a plurality of start signal ports STVs may be addedto provide an effective signal to the first input port IN1 of thedriving shift register unit of the first stage D_SR1. Furthermore, theplurality of the start signal ports STVs may provide an effective signalto a second input port IN2 of driving shift register units of each ofthe 1^(st) to N^(th) stages respectively. By adjusting timing ofeffective signals provided by the respective start signal ports STVs, asecond input port IN2 may receive an effective signal earlier than afirst input port IN1 at each stage of the driving shift register unit.

The timing of the effective signals provided by the respective startsignal ports STVs can be determined by the number N of the driving shiftregister unit. Correspondingly, the time interval between the effectivesignal received by a second input port and that by a first input port ofeach stage of the driving shift register unit is also related to N.Taking N=2 as an example, a process of driving the gate driving circuitincludes the following: in the first phase, an effective signal isprovided to the second input port IN2 of the driving shift register unitof the first stage D_SR1. In the second phase, an effective signal isprovided to the second input port IN2 of the driving shift register unitof the second stage D_SR2. In the third phase, an effective signal isprovided to the first input port IN1 of the driving shift register unitof the first stage D_SR1, and the second input port IN2 of the drivingshift register unit of the third stage D_SR3, respectively.

In one embodiment, as shown in FIG. 3, the gate driving circuit furthercomprises start shift register units of N stages connected in seriessuch as S_SR1, S_SR2, N is the total number of start shift registerunits. In one embodiment. An input terminal of a start shift registerunit of the first stage S_SR1 is connected to the start signal terminalSTV. An input terminal of a start shift register unit of the p stage maybe connected to an output terminal of a start shift register unit of the(p-1)-th stage. p may be an integer and 1<p≤N. As such, after the startsignal terminal STV inputs a start signal, each stage of the start shiftregister units sequentially outputs an effective signal. The secondinput port IN2 of the driving shift register unit of the first stageD_SR1 is connected to the start signal terminal SW The first input portIN1 of the driving shift register unit D_SR1 of the first stage isconnected to the output terminal OUT of the start shift register unit ofthe N stage. In other words, the N stages of the start shift registerunits are arranged before the driving shift register units. The stage atwhich a start shift register unit is designated is determined by theorder of the start shift register unit located in the N stages of startshift register units. It should be understood that the order of a startshift register unit is determined by the order of the start shiftregister unit located in the N stages of the start shift register units.The order of a driving shift register unit is determined by the order ofthe driving shift register unit located in all the driving shiftregister units.

In one embodiment, an input terminal of a start shift register unit ofthe first stage may be connected to the start signal terminal. A secondinput port of the driving shift register unit of the first stage may beconnected to the start signal terminal. A first input port of thedriving shift register unit of the first stage may be connected to anoutput terminal of the start shift register unit of the Nth stage. Asecond input port of the driving shift register unit of the q-th stagemay be connected to an output terminal of the start shift register unitof the (q−1) stage. q may be an integer and 1<q<N+1.

FIG. 4 shows a signal timing diagram during operation of the gatedriving circuit of FIG. 3 according to one embodiment of the presentinvention. When driving the gate driving circuit, it is only necessaryto provide a start signal to the start signal terminal STV in the firstphase. Specifically, in the case of N=2, as shown in FIG. 4, after thestart signal terminal STV receives a start signal in the first phase,the start shift register unit S_SR1 of the first stage outputs aneffective signal in the second phase. The start shift register unitS_SR2 of the second stage outputs an effective signal in the thirdphase. As such, the second input port IN2 of the driving shift registerunit of the second stage D_SR2 receives an effective signal in thesecond phase. The first input port IN1 of the driving shift registerunit of the first stage D_SR1 and the second input port IN2 of thedriving shift register unit of the third stage D_SR3 receive aneffective signal respectively in the third phase. Thus, the drivingshift register unit of the first stage D_SR1 outputs an effectivesignal, which is a second effective signal v2, in the second phase, andoutputs another effective signal, which is a first effective signal v1,at the fourth phase.

For the driving shift register unit of the second stage D_SR2, thesecond input port IN2 receives an effective signal outputted from thestart shift register unit of the first stage S_SR1 in the second phase,and the first input port receives the first effective signal outputtedBona the driving shift register unit of the first stage D_SR1 in thefourth phase. Thus, the driving shift register unit of the second stageD_SR2 outputs an effective signal, which is a second effective signalv2, in the third phase, and outputs an effective signal, which is afirst effective signal v1, in the fifth stage.

For the driving shift register unit of the third stage D_SR3, the secondinput port IN2 receives an effective signal outputted horn the startshift register unit of the second stage S_SR2 in the third phase, andthe first input port IN1 receives the first effective signal outputtedfrom the driving shift register unit of the second stage D_SR2 in thefifth phase. Thus, the driving shift register unit of the third stageoutputs an effective signal, which is a second I a significant signalv2, in the fourth phase, and outputs another effective signal, which isa first effective signal v1, in the sixth phase.

For the driving shift register unit of the fourth stage D_SR4, thesecond input port IN2 receives an effective signal outputted from thedriving shift register unit of the first stage D_SR1 in the second andfourth phases respectively. The first input port IN1 receives the firsteffective signal outputted from the driving shift register unit of thethird stage D_SR3 in the sixth phase. Therefore, the driving shiftregister unit of the fourth stage D_SR4 outputs two effective signals,which are the second effective signals v2, in the third and fifth phasesrespectively, and outputs another effective signal, which is the firsteffective signal v1, in the seventh phase. Likewise, hereafter, eachstage of the driving shift register unit outputs three effectivesignals, wherein the first two are second effective signals and thethird is a first effective signal. That is, pixel units of thecorresponding rows are pre-charged twice before the display, andpolarity of the signals written to the pixel units timing these, twopre-charge is the same.

The gate driving circuit may also be applied to a display device ofanother dot inversion mode. That is, N is another integer. The drivingprinciple is similar to that when N=2, and is not repeatedly describedhere.

As described above, when the display device employs the dot inversiondriving mode as shown in FIG. 2, that is, polarity of two adjacent pixelunits in any column is opposite. As such, N can be 2, 4, 6, or otherquantities.

For the dot inversion drive mode in FIG. 2, the interval between thetiming at which a second effective signal is received and the timing atwhich a first effective signal is received by a pixel unit is relativelyshort. That is, after the pixel unit receives the corresponding datasignal in the pre-charge phase, it takes only a short time to receivethe data signal for display.

The shift register unit may further comprise a reset terminal Reset. Theshift register unit here maybe a driving shift register unit or a startshill register unit. The shift register unit is used for outputting anineffective signal when it receives an effective signal at the resetterminal Reset. As shown in FIG. 3, in start shift register units of anytwo adjacent stages, the reset terminal Reset of the start shiftregister unit of the lower stage is connected with the output terminalof the start shift register unit of the higher stage. The reset terminalReset of the start shift register unit of the last stage is connected tothe output terminal OUT of the driving shift register unit of the firststage D_SR1. For driving shift register units of any two adjacentstages, the reset terminal of the driving shift register unit of thelower stage is connected to the output terminal OUT of the driving shiftregister unit of the higher stage. As such, after the driving shiftregister unit of each stage outputs a first effective signal to displaythe corresponding row of pixel units, it does not output any effectivesignals any more. Accordingly, the display of the corresponding row ofpixel units is not affected when data signals are written into the nextrow of pixel units for display.

FIG. 5 shows a block diagram of a module structure of a shift registerunit according to one embodiment of the present invention. The shiftregister unit here maybe a driving shift register unit or a start shiftregister unit. As shown in FIG. 5, the shift register unit furtherincludes a first clock signal CLKA, a second clock signal CLKB, anineffective signal terminal VSS, an input module 10, a pull-up module20, a reset module 30, and a pull-down module 40.

The input module 10 is connected to the input terminal IN of the shiftregister unit and the pull-up node PU respectively. The input module 10is used for providing an effective signal to the pull-up node PU when aneffective signal is received at the input terminal IN. The pull-up nodePU is a connection node of the input module 10 and the pull-up module20. In the driving shift register unit, that the input module 10 isconnected to the input terminal IN means. that the input module isconnected to both the first input port IN1 and the second input portIN2, When at least one of the first input port IN1 and the second inputport IN2 receives an effective signal, it can be regarded that the inputterminal IN of the driving shift register unit receives an effectivesignal.

The pull-up module 20 is connected to the pull-up node PU, the firstclock signal terminal CLKA, and the output terminal OUT of the shiftregister unit, respectively. The pull-up module 20 is used forelectrically connecting the first clock signal CLKA and the outputterminal OUT when the pull-up node PU receives an effective signal.

The reset module 30 is connected to the reset terminal Reset, thepull-up node PU, the output terminal OUT, and the ineffective signalterminal VSS, respectively. The reset module 30 is used for electricallyconnecting the output terminal OUT of the shift register unit and thepull-up node PU to the ineffective signal terminal VSS respectively whenthe reset terminal Reset receives an effective signal. The speed atwhich the reset module 30 electrically connects the pull-up node PU andthe ineffective signal terminal VSS should be smaller than the speed atwhich the input module 30 provides an effective signal to the pull-upnode PU when the input terminal IN receives an effective signal. This isto ensure that in the driving shift register unit, when one or both ofthe first input port IN1 and the second input port IN2 receive aneffective signal and the reset terminal Reset receives an effectivesignal, the pull-up node PU can still be at an effective potential.

The pull-down module 40 is connected to the second clock signal terminalCLKB, the pull-up node PU, and the output terminal OUT of the shiftregister unit, respectively. The pull-down module 40 is used forelectrically connecting the pull-up node PU and the output terminal OUTto the ineffective signal terminal VSS respectively when the secondclock signal CLKB receives an effective signal. The speed at which thepull-down module 40 electrically connects the pull-up node PU to theineffective signal tut urinal VSS should be less than the speed at whichthe input module 30 provides an effective signal to the pull-up node PUwhen the input terminal IN receives an effective signal. This is toensure that the pull-up node PU can reach an effective potential whenboth the second clock signal terminal CLKB and the input terminal IN ofthe shift register unit receive an effective signal.

FIG. 6 shows a schematic structural view of a start shift register unitaccording to one embodiment of the present invention. FIG. 8 shows aschematic structural view of a driving shift register unit according toone embodiment of the present invention. As shown in FIG. 6, the inputmodule 10 of the start shift register unit includes a fourth transistorM4. The gate and the first terminal of the fourth transistor M4 areconnected to the input terminal IN of the start shift register unit. Thesecond terminal of the fourth transistor M4 is connected to the pull-upnode PU of the start shift register unit.

As shown in FIG. 8, the input module 10 of the driving shift registerunit includes a first transistor M1, a second transistor M2, and a thirdtransistor M3. The gate and the first terminal of the first transistorM1 are connected to the first input port IN1 respectively. The gate andthe first terminal of the second transistor M2 are connected to thesecond input port IN2 respectively. The second terminal of the firsttransistor M1 is connected to the second terminal of the secondtransistor M2. The first terminal and the gate of the third transistorM3 is connected to the second terminal of the second transistor M2respectively. The second terminal of the third transistor M3 isconnected to the pull-up node PU of the driving shift register unit.

As shown in FIG. 6 and FIG. 8, the pull-up module 20 includes a fifthtransistor M5 and a storage capacitor C1. The first terminal of thestorage capacitor C1 is connected to the pull-up node PU of the shiftregister unit. The second terminal of the storage capacitor C1 isconnected to the output terminal OUT of the shift register unit. Thegate of the fifth transistor M5 is connected to the first terminal ofthe storage capacitor C1. The first terminal of the fifth transistor MSis connected to the first clock signal terminal CLKA. The secondterminal of the fifth transistor M5 is connected to the output terminalOUT of the shift register unit.

As shown in FIG. 6 and FIG. 8, the reset module 30 includes a sixthtransistor M6 and a seventh transistor M7. The gate of the sixthtransistor M6 and the gate of the seventh transistor M7 are connected tothe reset terminal Reset respectively. The first terminal of the sixthtransistor M6 is connected to the pull-up node PU. The first terminal ofthe seventh transistor is connected to the corresponding outputterminal. The second terminal of the sixth. transistor M6 and the secondterminal of the seventh transistor M7 are connected to the ineffectivesignal terminal VSS respectively. When the reset terminal receives aneffective signal, the sixth transistor and the seventh transistor areturned on, so that the pull-up node and the output terminal of the shiftregister unit are electrically connected to the ineffective signalterminal respectively. The width-length ratio of the sixth transistor,the tenth transistor, the third transistor, and the thirteenthtransistor should satisfy that when the input terminal receives an.effective electrical potential and the four transistors are turned on atthe same time, the speed at which the pull-up node receives theeffective electrical potential should be greater than the speed at whichthe pull-up node is electrically connected with the ineffective signal.

As shown in FIG. 6 and FIG. 8, the pull-down module 40 includes aneighth transistor M8, a ninth transistor M9, a tenth transistor M10, aneleventh transistor M11, a twelfth transistor M12, a thirteenthtransistor M13, a fourteenth transistor M14, and a fifteenth transistorM15. The gate of the thirteenth transistor M13 is connected to thesecond clock signal terminal CLKB. The first terminal of the thirteenthtransistor M13 is connected to the input terminal IN of the shiftregister unit. The second terminal of the thirteenth transistor M13 isconnected to the pull-up node PU. The gate and the first terminal of theninth transistor M9 are connected to the second clock signal CLKBrespectively. The second terminal of the ninth transistor M9 isconnected to the gate of the fifteenth transistor M15, and theconnection node thereof forms the pull-down control node PD_CN. Thefirst, terminal of the fifteenth transistor M15 is connected to thesecond dock signal CLKB. The second terminal of the fifteenth transistorM15 is connected to the first terminal of the fourteenth transistor M14,and the connection node thereof forms the pull-down node PD. The gate ofthe fourteenth transistor M14 is connected to the pull-up node PU. Thesecond terminal of the fourteenth transistor M14 is connected to theineffective signal terminal VSS. The gate of the eighth transistor M8 isconnected to the pull-up node PU. The first terminal of the eighthtransistor M8 is connected to the gate of the fifth transistor M5. Thesecond terminal of the eighth transistor M8 is connected to theineffective signal terminal VSS. The gate of the tenth transistor M10and the gate of the eleventh transistor M11 are connected to the secondterminal of the fifteenth transistor M15 respectively. The secondterminal of the tenth transistor M10 and the second terminal of theeleventh transistor M11 are both connected to the ineffective signalterminal VSS respectively. The first terminal of the tenth transistorM10 is connected to the pull-up node PU. The first terminal of theeleventh transistor M11 is connected to the output terminal OUT of theshift register unit. The gate of the twelfth transistor M12 is connectedto the second clock signal terminal CLKB. The first terminal of thetwelfth transistor M12 is connected to the output terminal OUT of theshift register unit. The second terminal of the twelfth transistor M12is connected to the ineffective signal terminal VSS.

In one embodiment, each of the transistors is an N-type thin filmtransistor. Accordingly, the effective signal is a high-level signal,and the ineffective signal is a low-level signal. In another embodiment,each of the transistors may be a P-type thin film transistor.Accordingly, the effective signal is a low level signal, and theineffective signal a high level signal.

FIG. 7 shows a signal timing diagram in operation of the start shiftregister unit of FIG. 6 according to one embodiment of the presentinvention. The operation of the start shift register unit will bedescribed below with reference to FIG. 6 and FIG. 7. Each transistor isan N-type thin film transistor and the effective signal is a high levelsignal. In the t1 phase, the input terminal IN is inputted an effectivesignal. The first clock signal terminal CLKA is inputted an ineffectivesignal. At this time, the fourth transistor M4 is turned on and thepull-up node PU receives an effective signal. At the same time, theeighth transistor M8 and the fourteenth transistor M14 are turned on, sothat the pull-down control node PD_CN and the pull-down node PD receivean ineffective signal respectively. Furthermore, the fifth transistor M5is turned on so that the first clock signal terminal CLKA and the outputterminal OUT are electrically connected. The output terminal OUT outputsan ineffective signal.

In the t2 phase, the input terminal IN is inputted an ineffectivesignal. The first clock signal terminal CLKA is inputted an effectivesignal. The second clock signal terminal CLKB is inputted an ineffectivesignal. At this time, the fourth transistor M4 is turned off. Thepotential of the pull-up node PU is further raised by a bootstrap actionof the storage capacitor C1, so that the fifth transistor M5 is turnedon. As such, the first clock signal terminal CLKA is electricallyconnected with the output terminal OUT. The output terminal OUT outputsan effective signal.

In the t3 phase, the reset terminal Reset is inputted an effectivesignal, the first clock signal terminal CLKA is inputted an ineffectivesignal, and the second clock signal terminal CLKB is inputted aneffective signal, At this time, the twelfth transistor M12 is turned. onso that the output terminal OUT and the ineffective signal terminal VSSare electrically connected. At the same time, the sixth transistor M6and the seventh transistor M7 are turned on so that both the pull-upnode PU and the output terminal OUT are electrically connected with theineffective signal terminal respectively. At the same time, the ninthtransistor M9, the thirteenth transistor M13, and the fifteenthtransistor M15 are turned on. The pull-down node PD receives aneffective signal so that the tenth transistor M10 and the eleventhtransistor M11 are turned on. The pull-up node PU and the outputterminal OUT may also be electrically connected with the ineffectivesignal terminal VSS respectively. The output terminal OUT outputs anineffective signal.

In the t4 phase, the first clock signal terminal CLKA is inputted aneffective signal. The second clock signal terminal CLKB and the inputterminal IN are inputted an ineffective signal respectively. At thistime, the fourth transistor M4, the ninth transistor M9, and thefifteenth transistor M15 are turned off, but the fourteenth transistorM14, the eleventh transistor M11, and the tenth transistor M10 leakcurrent. As such, the pull-down node PD and the ineffective signalterminal are electrically connected. At the same time, the pull-up nodePU and the output terminal OUT maintain the ineffective potential.

In the t5 phase, the first clock signal terminal CLKA is inputted anineffective signal and the second clock signal terminal CLKB is inputtedan effective signal. At this time, the twelfth transistor M12, thethirteenth transistor M13, the ninth transistor M9, and the fifteenthtransistor M15 are turned on. The pull-down node PD receives aneffective signal so that both the pull-up node PU and the outputterminal OUT are electrically connected with the ineffective signalterminal VSS. Then, the t4 and the t5 phases are repeated, and theoutput terminal OUT continues to output a low level until the inputterminal IN is inputted an effective signal again.

FIG. 9 is a signal timing diagram in operation of the driving shiftregister of FIG. 8 according to one embodiment of the present invention.The difference between the operation of the driving shift register unitand that of the start shift register is that the input terminal IN ofthe driving shift register unit receives an effective signal at leasttwice and the output terminal OUT of the driving shift register unitoutputs at least two effective signals. Take the effective signal beingreceived at least twice at the input terminal IN of the driving shiftregister unit as an example, as shown in FIG. 9, in the t1 phase, atleast one of the first input port IN1 and the second input port IN2 isinputted with an effective signal, so that at least one of the firsttransistor M1 and the second transistor M2 is turned on. As a result,the third transistor M3 is turned on and the pull-up node PU receives aneffective signal. The states of the remaining transistors are the sameas those in the start shift register unit in the t1 phase, in the t2phase, the first transistor M1 and the second transistor M2 are turnedoff and the states of the remaining transistors and the potential ofeach node are the same as those in the start shift register unit in thet2 phase. In the t3 phase, at least one of the first input port IN1 andthe second input port IN2 is inputted with an effective signal, so thatat least one of the first transistor M1 and the second transistor M2 isturned on. As a result, the third transistor M3 is turned on. Thepull-up node PU receives an effective potential. At the same time, thereset terminal Reset is inputted an effective signal so that the pull-upnode PU and the output terminal OUT are electrically connected to theineffective signal terminal VSS respectively. Further, the speed atwhich the pull-up node PU and the ineffective signal terminal VSS areelectrically connected is smaller than the speed at which the pull-upnode PU receives the effective signal, so that the pull-up node PU inthe t3 phase can reach the effective potential, and the output terminalOUT outputs an ineffective In the t4 phase, similar to the t2 phase, theoutput terminal OUT outputs an effective signal. After the t4 phase, thefirst transistor M1 and the second transistor M2 of the driving shiftregister unit remain off The states of the remaining transistors are thesame as those in the start shift register unit after the t3 phase. Assuch, the driving shift register unit continues to output an ineffectivesignal after the t4 phase until an effective signal is inputted again tothe input terminal IN. Of course, the input terminal IN of the shiftregister unit can also receive an effective signal three times. In thiscase, the timings of signals are similar to those in FIG. 9 except thatthe output terminal OUT outputs three effective signals accordingly.

Further, as shown in FIG. 3, in order to facilitate provision of signalsto the first clock signal terminal CLKA and the second clock signalterminal CLKB of each of the shift a registering units, the gate drivingcircuit further includes a first clock supply terminal CLK1 and a secondclock supply terminal CLK2. The first clock supply terminal CLK1 and thesecond clock supply terminal CLK2 are used for providing clock signalswith opposite phases. The first clock signal terminals CLKA of the startshift register units of the odd-numbered stages and of the driving shiftregister units of the odd-numbered stages are connected to the firstclock supply terminal CLK1. The second clock signal terminals CLKB ofthe start shift register units of the odd-numbered stages and of thedriving shift register units of the odd-numbered stages are connected tothe second clock supply terminal CLK2. The first clock signal terminalsCLKA of the start shift register units of the even-numbered stages andof the driving shift register units of the even-numbered stages areconnected to the second clock supply terminal CLK2. The second clocksignal CLKB of the start shift register units of the even-numberedstages and of the driving shift register units of the even-numberedstages are connected to the first clock supply terminal CLK1. Of course,the gate driving circuit may also include an ineffective signal supplyterminal VSS′ for providing an ineffective signal. The ineffectivesignal supply terminal VSS′ may be connected to the ineffective signalterminal VSS of each shift register unit.

Another example of the present invention is a driving method of the gatedriving circuit according to one embodiment of the present invention.The driving method comprises the following driving steps at each cycleof display:

An effective signal is sequentially provided to the second input portIN2 of driving shift register units of theist to N-th stagesrespectively. Then, an effective signal is simultaneously provided tothe first input port of the driving shift register unit of the firststage and the second input port of the driving shift register unit ofthe (N+1)-th stage respectively.

As described above, the effective signal outputted when the drivingshift register unit receives an effective signal at its second inputport is referred to as the second effective signal. And the effectivesignal outputted when the first input port receives the effective signaland the second input port does not receive the effective signal isreferred to as the first effective signal. Then, each stage of thedriving shift register unit outputs a second effective signal earlierthan a first effective signal. In addition, the second input port of thedriving shift register unit of the m-th stage and the first input portof the driving shift register unit of the (m−N)-th stage are bothconnected to the output terminal of the driving shift register unit ofthe (m−N−1)th stage, Thus, when the driving shift register unit of the(m−N−1)-th stage outputs the first effective signal, the first inputport of the driving shift register unit of the (m−N)-th stage and thesecond input port of the driving shift register unit of the nth stagesimultaneously receive an effective signal. As a result, the drivingshift register unit of the (m−N)-th stage outputs a first effectivesignal to turn on the pixel units of the (m−N)-th row. At this time, thesource driving circuit can write data to the pixel units of the (m−N)-throw, so that the pixel units of the (m−N)-th row is displayed. At thesame time, the driving shift register unit of the m-th stage outputs asecond effective signal to turn on pixel units of the m-th row. As such,the data signals which are written to the pixel units of the (m−N)-throw are also written in the pixel units of the m-th row, therebypre-charging the pixel units of the m-th row. Since polaritydistribution of the pixel units of the in-th row and of the (m−n)-th rowis the same, therefore, the signals on the pixel units of the m-th rowat the time of pre-charging have the same polarity as the signals whichare later written to the pixel units of the m-th row for display. Thus,reverse pre-charging does not occur here, and the display effect can beguaranteed while the speed of writing data signals is increased.

In another embodiment, the gate driving circuit includes a start signalterminal, a first clock supply terminal, and a second clock supplyterminal. The shift register unit includes a first clock signal terminaland a second clock signal terminal. The plurality of the shift register.units further comprise N stages of the start shift register unitsconnected in series. The driving method of the gate driving circuitincludes the followings.

Two clock signals having opposite phases are provided to the first clocksupply terminal and the second clock supply terminal, respectively. Atthe initial phase, a start signal is provided to the start signalterminal. Polarity of each of the clock signals in two adjacent phasesare opposite. The clock signal of the first clock supply terminal is anineffective signal at the initial phase. As such, an effective signal isprovided sequentially to the second input ports of driving shiftregister units of the 1st to N-th stages. Furthermore, the first inputport. IN1 of the driving shift register unit of the first stage and thesecond input port IN2 of the driving shift register unit of the (N+1)-thstage receive an effective signal simultaneously after the second inputport IN2 of the driving shift register unit of the Nth stage receives aneffective signal.

In one embodiment, for the dot inversion driving method as in FIG. 2,the gate driving circuit has the structure shown in FIG. 3, that is,N=2. The operation principle of the gate driving circuit in FIG. 3 willbe described in detail in the following part based on the operationprinciple of the start shift register unit and the driving shiftregister unit.

As shown in FIG. 4, in the first phase, which is the initial phase, thestart signal terminal STV provides an effective signal. For the startshift register unit of the first stage S_SR1, its input terminal INreceive an effective signal in the second phase so that the pull-up nodePU receives an effective signal. In the second phase, the first clocksignal terminal CLKA of the start shift register unit of the first stageS_SR1 receives the effective signal provided by the first clock supplyterminal CLK1. At the same time, the pull-up module 20 electricallyconnects the output a terminal OUT to the first clock signal CLKA due tothe effective potential at the pull-up node PU. As a result, the outputterminal OUT outputs an effective signal. After the second phase, thestart shift register unit of the first stage S_SR1 continues to outputan ineffective signal until the next cycle of display.

For the start shift register unit of the second stage S_SR2, in thesecond phase, the input terminal IN of the start shift register unit ofthe second stage S_SR2 receives the effective signal outputted from thestart shift register unit S_SR1 of the first stage so that the pull-upnode PU of S_SR2 receives an effective signal. In the third phase, thefirst clock signal terminal CLKA of the start shift register unit of thesecond stage S_SR2 receives the effective signal provided by the secondclock supply terminal CLK2. At the same time, the output terminal OUT iselectrically connected to the first clock signal terminal CLKA andaccordingly outputs an effective signal. After the third phase, thestart shift register unit S_SR2 of the second stage continues to outputthe ineffective signal until the next cycle of display.

For the driving shift register unit D_SR1 of the first stage, in thefirst phase, the second input port 1142 of the driving shift registerunit of the first stage D_SR1 receives the effective signal of the startsignal terminal STV, so that the pull-up node PU of the driving shiftregister unit D_SR1 of the first stage receives an effective signal. Inthe second phase, the first clock signal terminal CLKA of the drivingshift register unit of the first stage D_SR1 receives the effectivesignal provided by the first clock supply terminal CLK1. At the sametime, the pull-up module 20 electrically connects the output terminalOUT to the first clock signal CLKA. due to the effective potential atthe pull-up node PU so that the output terminal OUT outputs an effectivesignal, which is a second effective signal. In the third phase, thefirst input port IN1 of the driving shift registering unit of the firststage D_SR1 receives the effective signal outputted. from the startshift register unit S_SR2 of the second stage, so that the pull-up nodePU of the driving shift register unit of the first stage receives aneffective signal again. At the same time, the reset terminal and thepull-dower node PD of the driving shift register unit of the first stageD_SR1 receive an effective signal, so that the driving shift registerunit of the first stage D_SR1 outputs an ineffective signal. In thefourth phase, the first clock signal terminal CLKA of the driving shiftregister unit of the first stage D_SR1 receives the effective signalprovided by the first clock supply terminal CLK1. At the same time, thepull-up module 20 electrically connects the output terminal OUT to thefirst clock signal CLKA due to the effective potential at the pull-upnode PU. As a result, the output terminal OUT outputs an effectivesignal, which is a first effective signal, After the fourth phase, thepull-down node PD of the driving shift register unit of the first stageD_SR1 is alternately at an effective potential and an ineffectivepotential. The pull-up node PU and the output terminal OUT no longerreceive an effective signal. As a result, the output terminal OUTcontinues to output an ineffective signal until the next cycle ofdisplay.

For the driving shift register unit of the second stage D_SR2, in thesecond phase, the second input port IN2 of the driving shift registeringunit of the second stage D_SR2 receives the effective signal outputtedfrom the start shift register unit of the first stage S_SR1 so that thepull-up node PU of the driving shift register unit of the second stageD_SR2 receives an effective signal. In the third phase, the first clocksignal terminal CLKA of the driving shift register unit of the secondstage D_SR2 receives the effective signal provided by the second clocksupply terminal CLK2, At the same time, the pull-up module 20electrically connects the output terminal OUT to the first clock signalCLKA due to the effective potential at the pull-up node PU, As a result,the output terminal OUT outputs an effective signal, which is a secondeffective signal. in the fourth phase, the first input port IN1 of thedriving shift register unit of the second stage D_SR2 receives the firsteffective signal outputted from the driving shift register unit of thefirst stage D_SR1, so that the pull-up node PU of the driving shiftregister unit of the second stage D_SR2 receives an effective signalagain. In the fifth phase, the first clock signal terminal CLKA of thedriving shift register unit of the second stage receives an effectivesignal. The pull-up module 20 electrically connects the output terminalOUT to the first clock signal CLKA. As a result, the output terminal OUToutputs an effective signal, which is a first effective signal. Afterthe fifth phase, the output terminal OUT of the driving shift registerunit of the second stage D_SR2 continues to output an ineffective signaluntil the next cycle of display.

For the driving shift register unit of the third stage, in the thirdphase, the second input port IN2 of the driving shift register unit ofthe third stage D_SR3 receives the second effective signal outputtedfrom the, start shift mister unit of the second stage S_SR2, so that thepull-up node PU of the driving shift: register unit of the third stageD_SR3 receives an effective signal. In the fourth phase, the first clocksignal terminal CLKA of the driving shift register unit of the thirdstage D_SR3 receives an effective signal provided by the first clocksupply terminal CLK1. At the same time, the pull-up module 20electrically connects the output terminal OUT to d the first clocksignal CLKA due to the effective potential at the pull-up node PU. As aresult, the output terminal OUT outputs an effective signal, which is asecond effective signal. In the fifth phase, the first input port IN2 ofthe driving shift register unit of the third stage D_SR3 receives thefirst effective signal outputted from the driving shift register unit ofthe second stage D_SR2, so that the pull-up node PU of the driving shiftregister unit of the third stage D_SR3 receives an effective signalagain. In the sixth phase, the first clock signal CLKA of the drivingshift register unit of the third stage D_SR3 receives the effectivesignal provided by the first clock supply terminal CLK1. At the sametime, the pull-up module 20 electrically connects the output terminalOUT to the first clock signal CLKA due to the effective potential at thepull-up node PU. As a result, the output terminal OUT outputs aneffective signal. After the sixth phase, the output terminal OUT of thedriving shift register unit of the third stage D_SR3 continues to outputan ineffective signal until the next cycle of display.

For the driving shift register unit of the fourth stage D_SR4, in thesecond phase and the fourth phase, the second input port IN2 of thedriving shift register unit of the fourth stage D_SR4 receives thesecond effective signal and the first effective signal outputted fromthe driving shift register unit of the first stage D_SR1 respectively.Similar to the driving shift register unit of the second stage D_SR2,the driving shift register unit of the fourth stage outputs twoeffective signals in the third and fifth phases respectively. The twoeffective signals are both outputted after the second input port IN2 ofthe driving shift register unit of the fourth stage D_SR4 receives theeffective signal and accordingly regarded as the second effectivesignals. In the sixth phase, the first input port IN1 of the drivingshift register unit of the fourth stage D_SR4 receives the firsteffective signal outputted from the driving shift register unit of thethird stage D_SR3, so that the pull-up node PU receives an effectivesignal for the third time. In the seventh phase, the first clock signalterminal CLKA of the driving shift register unit of the fourth stageD_SR4 receives the effective signal provided by the second clock supplyterminal CLK2. At the same time, the pull-up module 20 electricallyconnects the output terminal OUT to the first dock signal CLKA due tothe effective potential at the pull-up node PU. As a result, the outputterminal OUT outputs an effective signal, which is a first effectivesignal. After that. the output terminal OUT of the driving shiftregister unit of the fourth stage D_SR4 continues to output aninflective signal until the next cycle of display.

Likewise, each of the driving shift register units of the fifth andlater stages outputs three effective signals. Among the three effectivesignals, the first two effective signals can be regarded as secondeffective signals and the third effective signal can be regarded as afirst effective signal.

It can be seen that when the driving shift register unit of the thirdstage outputs a second driving signal to pre-charge the pixel units ofthe third row, the driving shift register unit of the first stageoutputs a first driving signal to write data signals to the pixel unitsof the first row for display. The signals received by the pixel units ofthe third row for pre-charging are the same as the signals received bythe pixel units of the first row for display, and polarity distributionsof the first and third rows of pixel units are the same. Therefore, thepixel units of the third row can be pre-charged before the display,thereby increasing the speed of writing signals during the display.Similarly, for each of the driving shift register units of the fourthand subsequent stages, when each second effective signal is outputted,the corresponding row of pixel units is pre-charged. Furthermore,polarity of the signals written to the pixel units of a row at the timeof pre-Charge is the same as that of the signals required for the samerow to be displayed later, thereby increasing the speed of writingsignals during the display.

Another example of the present invention is a display substrate. Thedisplay substrate comprises a plurality of rows of pixel units and thegate driving circuit according to one embodiment of the presentinvention. Each of the driving shift register units of the gate drivingcircuit, corresponds with one of the plurality of rows of the pixelunits. Specifically, a plurality of gate lines and a plurality of datalines are provided on a base substrate of the display substrate. Theplurality of gate lines and the plurality of data lines intersect witheach other to define a plurality of pixel units. The gate drivingcircuit may be disposed on the base substrate, and the output terminalof each of the shift register units is connected to the gate line of thecorresponding row of pixels.

Another example of the present invention is a display device. Thedisplay device includes a display substrate according to one embodimentof the present invention. In the gate driving circuit, when the drivingshift register unit of the (m−N)-th stage outputs a first effectivesignal, the driving shift register unit of the in-th stage outputs asecond effective signal. Therefore, when the (m−N)-th row of pixel unitsis displayed, the m-th row of pixel units can be pre-charged, therebyimproving the writing speed of signals for the m-th row of pixel unitsduring display. This facilitates production of a display device having alarge size and a high resolution. Furthermore, because polaritydistributions of the pixel units of the m-th row and the (m−N)-th roware the same, the polarity of the signals of the m-th row of pixel unitsat the time of pre-charging is the same as the polarity of the signalsof the row of pixel units written subsequently for display. Therefore,reverse pre-charging does not occur, and the display effect can beensured while writing speed the data signals is increased.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

A list of abbreviation in the present application is shown:

S_SR1, S_S2: Start shift register

D_SR1 to D_SR4: Driving shift register

IN: input terminal

IN1: first input terminal

IN2: second input terminal

OUT: output terminal

CLKA: first clock signal terminal

CLKB: second clock signal terminal

CLK1: first clock supply terminal

CLK2: second clock supply terminal

Reset: reset terminal

VSS: ineffective signal terminal

STV: start signal terminal

10: input module

20: pull-up module

30: reset module

40: pull-down module

M1˜M15: first transistor to fifteenth transistor

PU: pull-up node

PD: pull-don node

PD_CN: pull-down control node.

1. A gate driving circuit comprising: x stages of driving shift registerunits connected in, series, each of the driving shift register unitscomprising an input terminal, an output terminal, and a reset terminal,the input terminal comprising a first input port and a second inputport, wherein a first input port of a driving shift register unit of them-th stage is connected to an output terminal of a driving shiftregister unit of the (m−1)-th stage, and a second input port of thedriving shift register unit of the m-th stage is connected to an outputterminal of a driving shift register unit of the (m−N−1)-th stage,wherein N is an integer greater than 1, x is an integer, in is aninteger, and N+1<m≤x.
 2. The gate driving circuit according to claim 1,wherein a row of pixel units driven by the driving shift register unitof the m-th stage have the same polarity distribution as a row of pixelunits driven by a driving shift register unit of the (m−N)-th stage. 3.The gate driving circuit according to claim 1, further comprising: Nstages of start shift register units connected in series, and wherein aninput terminal of a start shift register unit of the p stage isconnected to an output terminal of a start shift register unit of the(p−1)-th stage, wherein p is an integer and 1<p≤IN.
 4. The gate drivingcircuit according to claim 3, wherein N is
 2. 5. The gate drivingcircuit according to claim 3, further comprising a start signalterminal, wherein an input terminal of a start shift register unit ofthe first stage is connected to the start signal terminal, a secondinput port of a driving shift register unit of the first stage isconnected to the start signal terminal, a first input port of thedriving shift register unit of the first stage is connected to an outputterminal of a start shift register unit of the Nth stage, a second inputport of a driving shift register unit of the q-th stage is connected toan output terminal of a start shift register unit of the (q−1) stage,wherein q is an integer and 1<q≤N+1.
 6. The gate driving circuitaccording to claim 5, wherein an output terminal of the start shiftregister unit of the p stage is connected to a reset terminal of thestart shift register unit of the (p−1)-th stage, a reset terminal of thestart shift register unit of the N stage is connected to an outputterminal of a driving shift register unit of the first stage, andwherein an output terminal of the driving shift register unit of thein-th stage is connected to a reset terminal of the driving shiftregister unit of the (m−1) flu stage.
 7. The gate driving circuitaccording to claim 1, each of the driving shift register units isconfigured to output an effective signal after at least one of the firstinput port and the second input port receives an effective signal. 8.The gate driving circuit according to claim 7, further comprising afirst clock supply terminal and a second clock supply terminal, thefirst clock supply terminal and the second clock supply terminalconfigured to provide clock signals with opposite phases, wherein afirst clock signal terminal of a start shift register unit of theodd-numbered stage and that of a driving shift register unit of theodd-numbered stage are connected to the first clock supply terminalrespectively, a second clock signal terminal of the start shift registerunit of the odd-numbered stage and that of the driving shift registerunit of the odd-numbered stage are connected to the second clock supplyterminal respectively, a first clock signal terminal of a start shiftregister unit of the even-numbered stage and that of a driving shiftregister unit of the even-numbered stage are connected to the secondclock supply terminal respectively, and a second clock signal terminalof the start shift register unit of the even-numbered stage and that ofthe driving shift register unit of the even-numbered stage are connectedto the first clock supply terminal respectively.
 9. The gate drivingcircuit according to claim 3, wherein each of the start shift registerunits includes an input module, a pull-up module, a reset module, and apull-down module.
 10. The gate driving circuit according to claim 9,wherein the input module of the start shift register unit includes afourth transistor, a gate and a first terminal of the fourth transistorare connected to the input terminal of the start shift register unit,and a second terminal of the fourth transistor is connected to a pull-upnode of the start shift register unit.
 11. A display substratecomprising a plurality of rows of pixel units and the gate drivingcircuit according to claim 1, each of the driving shift register unitscorresponds to one of the plurality of rows of the pixel unitsrespectively.
 12. A display device comprising the display substrateaccording to claim
 11. 13. A driving method of the gate driving circuitaccording to claim 1, comprising: in each cycle of display cycle,providing an effective signal to the input terminal of the start shiftregister unit of the first stage, and providing an effective signal tothe second input port of the driving shift register unit of the firststage.
 14. The driving method according to claim 13, the driving methodfurther comprising: providing two clock signals with opposite phases bythe first clock supply terminal and the second clock supply terminalrespectively.
 15. (canceled)
 16. (canceled)
 17. (canceled) 18.(canceled)
 19. (canceled)
 20. (canceled)